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<div class="fragment"><div class="line"><a id="l00001" name="l00001"></a><span class="lineno">    1</span><span class="comment">// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT</span></div>
<div class="line"><a id="l00002" name="l00002"></a><span class="lineno">    2</span> </div>
<div class="line"><a id="l00008" name="l00008"></a><span class="lineno">    8</span><span class="preprocessor">#ifndef _HARDWARE_STRUCTS_SCB_H</span></div>
<div class="line"><a id="l00009" name="l00009"></a><span class="lineno">    9</span><span class="preprocessor">#define _HARDWARE_STRUCTS_SCB_H</span></div>
<div class="line"><a id="l00010" name="l00010"></a><span class="lineno">   10</span> </div>
<div class="line"><a id="l00015" name="l00015"></a><span class="lineno">   15</span><span class="preprocessor">#include &quot;<a class="code" href="address__mapped_8h.html">hardware/address_mapped.h</a>&quot;</span></div>
<div class="line"><a id="l00016" name="l00016"></a><span class="lineno">   16</span><span class="preprocessor">#include &quot;hardware/regs/m0plus.h&quot;</span></div>
<div class="line"><a id="l00017" name="l00017"></a><span class="lineno">   17</span> </div>
<div class="line"><a id="l00018" name="l00018"></a><span class="lineno">   18</span><span class="comment">// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus</span></div>
<div class="line"><a id="l00019" name="l00019"></a><span class="lineno">   19</span><span class="comment">//</span></div>
<div class="line"><a id="l00020" name="l00020"></a><span class="lineno">   20</span><span class="comment">// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the &quot;Go to Definition&quot; feature)</span></div>
<div class="line"><a id="l00021" name="l00021"></a><span class="lineno">   21</span><span class="comment">// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.</span></div>
<div class="line"><a id="l00022" name="l00022"></a><span class="lineno">   22</span><span class="comment">//</span></div>
<div class="line"><a id="l00023" name="l00023"></a><span class="lineno">   23</span><span class="comment">// Bit-field descriptions are of the form:</span></div>
<div class="line"><a id="l00024" name="l00024"></a><span class="lineno">   24</span><span class="comment">// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION</span></div>
<div class="line"><a id="l00025" name="l00025"></a><span class="lineno">   25</span> </div>
<div class="line"><a id="l00026" name="l00026"></a><span class="lineno"><a class="line" href="structarmv6m__scb__hw__t.html">   26</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span>{</div>
<div class="line"><a id="l00027" name="l00027"></a><span class="lineno">   27</span>    _REG_(M0PLUS_CPUID_OFFSET) <span class="comment">// M0PLUS_CPUID</span></div>
<div class="line"><a id="l00028" name="l00028"></a><span class="lineno">   28</span>    <span class="comment">// CPUID Base Register</span></div>
<div class="line"><a id="l00029" name="l00029"></a><span class="lineno">   29</span>    <span class="comment">// 0xff000000 [31:24] IMPLEMENTER  (0x41) Implementor code: 0x41 = ARM</span></div>
<div class="line"><a id="l00030" name="l00030"></a><span class="lineno">   30</span>    <span class="comment">// 0x00f00000 [23:20] VARIANT      (0x0) Major revision number n in the rnpm revision status: +</span></div>
<div class="line"><a id="l00031" name="l00031"></a><span class="lineno">   31</span>    <span class="comment">// 0x000f0000 [19:16] ARCHITECTURE (0xc) Constant that defines the architecture of the processor: +</span></div>
<div class="line"><a id="l00032" name="l00032"></a><span class="lineno">   32</span>    <span class="comment">// 0x0000fff0 [15:4]  PARTNO       (0xc60) Number of processor within family: 0xC60 = Cortex-M0+</span></div>
<div class="line"><a id="l00033" name="l00033"></a><span class="lineno">   33</span>    <span class="comment">// 0x0000000f [3:0]   REVISION     (0x1) Minor revision number m in the rnpm revision status: +</span></div>
<div class="line"><a id="l00034" name="l00034"></a><span class="lineno">   34</span>    io_ro_32 cpuid;</div>
<div class="line"><a id="l00035" name="l00035"></a><span class="lineno">   35</span> </div>
<div class="line"><a id="l00036" name="l00036"></a><span class="lineno">   36</span>    _REG_(M0PLUS_ICSR_OFFSET) <span class="comment">// M0PLUS_ICSR</span></div>
<div class="line"><a id="l00037" name="l00037"></a><span class="lineno">   37</span>    <span class="comment">// Interrupt Control and State Register</span></div>
<div class="line"><a id="l00038" name="l00038"></a><span class="lineno">   38</span>    <span class="comment">// 0x80000000 [31]    NMIPENDSET   (0) Setting this bit will activate an NMI</span></div>
<div class="line"><a id="l00039" name="l00039"></a><span class="lineno">   39</span>    <span class="comment">// 0x10000000 [28]    PENDSVSET    (0) PendSV set-pending bit</span></div>
<div class="line"><a id="l00040" name="l00040"></a><span class="lineno">   40</span>    <span class="comment">// 0x08000000 [27]    PENDSVCLR    (0) PendSV clear-pending bit</span></div>
<div class="line"><a id="l00041" name="l00041"></a><span class="lineno">   41</span>    <span class="comment">// 0x04000000 [26]    PENDSTSET    (0) SysTick exception set-pending bit</span></div>
<div class="line"><a id="l00042" name="l00042"></a><span class="lineno">   42</span>    <span class="comment">// 0x02000000 [25]    PENDSTCLR    (0) SysTick exception clear-pending bit</span></div>
<div class="line"><a id="l00043" name="l00043"></a><span class="lineno">   43</span>    <span class="comment">// 0x00800000 [23]    ISRPREEMPT   (0) The system can only access this bit when the core is halted</span></div>
<div class="line"><a id="l00044" name="l00044"></a><span class="lineno">   44</span>    <span class="comment">// 0x00400000 [22]    ISRPENDING   (0) External interrupt pending flag</span></div>
<div class="line"><a id="l00045" name="l00045"></a><span class="lineno">   45</span>    <span class="comment">// 0x001ff000 [20:12] VECTPENDING  (0x000) Indicates the exception number for the highest priority...</span></div>
<div class="line"><a id="l00046" name="l00046"></a><span class="lineno">   46</span>    <span class="comment">// 0x000001ff [8:0]   VECTACTIVE   (0x000) Active exception number field</span></div>
<div class="line"><a id="l00047" name="l00047"></a><span class="lineno">   47</span>    io_rw_32 icsr;</div>
<div class="line"><a id="l00048" name="l00048"></a><span class="lineno">   48</span> </div>
<div class="line"><a id="l00049" name="l00049"></a><span class="lineno">   49</span>    _REG_(M0PLUS_VTOR_OFFSET) <span class="comment">// M0PLUS_VTOR</span></div>
<div class="line"><a id="l00050" name="l00050"></a><span class="lineno">   50</span>    <span class="comment">// Vector Table Offset Register</span></div>
<div class="line"><a id="l00051" name="l00051"></a><span class="lineno">   51</span>    <span class="comment">// 0xffffff00 [31:8]  TBLOFF       (0x000000) Bits [31:8] of the indicate the vector table offset address</span></div>
<div class="line"><a id="l00052" name="l00052"></a><span class="lineno">   52</span>    io_rw_32 vtor;</div>
<div class="line"><a id="l00053" name="l00053"></a><span class="lineno">   53</span> </div>
<div class="line"><a id="l00054" name="l00054"></a><span class="lineno">   54</span>    _REG_(M0PLUS_AIRCR_OFFSET) <span class="comment">// M0PLUS_AIRCR</span></div>
<div class="line"><a id="l00055" name="l00055"></a><span class="lineno">   55</span>    <span class="comment">// Application Interrupt and Reset Control Register</span></div>
<div class="line"><a id="l00056" name="l00056"></a><span class="lineno">   56</span>    <span class="comment">// 0xffff0000 [31:16] VECTKEY      (0x0000) Register key: +</span></div>
<div class="line"><a id="l00057" name="l00057"></a><span class="lineno">   57</span>    <span class="comment">// 0x00008000 [15]    ENDIANESS    (0) Data endianness implemented: +</span></div>
<div class="line"><a id="l00058" name="l00058"></a><span class="lineno">   58</span>    <span class="comment">// 0x00000004 [2]     SYSRESETREQ  (0) Writing 1 to this bit causes the SYSRESETREQ signal to...</span></div>
<div class="line"><a id="l00059" name="l00059"></a><span class="lineno">   59</span>    <span class="comment">// 0x00000002 [1]     VECTCLRACTIVE (0) Clears all active state information for fixed and...</span></div>
<div class="line"><a id="l00060" name="l00060"></a><span class="lineno">   60</span>    io_rw_32 aircr;</div>
<div class="line"><a id="l00061" name="l00061"></a><span class="lineno">   61</span> </div>
<div class="line"><a id="l00062" name="l00062"></a><span class="lineno">   62</span>    _REG_(M0PLUS_SCR_OFFSET) <span class="comment">// M0PLUS_SCR</span></div>
<div class="line"><a id="l00063" name="l00063"></a><span class="lineno">   63</span>    <span class="comment">// System Control Register</span></div>
<div class="line"><a id="l00064" name="l00064"></a><span class="lineno">   64</span>    <span class="comment">// 0x00000010 [4]     SEVONPEND    (0) Send Event on Pending bit: +</span></div>
<div class="line"><a id="l00065" name="l00065"></a><span class="lineno">   65</span>    <span class="comment">// 0x00000004 [2]     SLEEPDEEP    (0) Controls whether the processor uses sleep or deep sleep...</span></div>
<div class="line"><a id="l00066" name="l00066"></a><span class="lineno">   66</span>    <span class="comment">// 0x00000002 [1]     SLEEPONEXIT  (0) Indicates sleep-on-exit when returning from Handler mode...</span></div>
<div class="line"><a id="l00067" name="l00067"></a><span class="lineno">   67</span>    io_rw_32 scr;</div>
<div class="line"><a id="l00068" name="l00068"></a><span class="lineno">   68</span>} <a class="code hl_struct" href="structarmv6m__scb__hw__t.html">armv6m_scb_hw_t</a>;</div>
<div class="line"><a id="l00069" name="l00069"></a><span class="lineno">   69</span> </div>
<div class="line"><a id="l00070" name="l00070"></a><span class="lineno">   70</span><span class="preprocessor">#define scb_hw ((armv6m_scb_hw_t *)(PPB_BASE + M0PLUS_CPUID_OFFSET))</span></div>
<div class="line"><a id="l00071" name="l00071"></a><span class="lineno">   71</span><span class="keyword">static_assert</span>(<span class="keyword">sizeof</span> (<a class="code hl_struct" href="structarmv6m__scb__hw__t.html">armv6m_scb_hw_t</a>) == 0x0014, <span class="stringliteral">&quot;&quot;</span>);</div>
<div class="line"><a id="l00072" name="l00072"></a><span class="lineno">   72</span> </div>
<div class="line"><a id="l00073" name="l00073"></a><span class="lineno">   73</span><span class="preprocessor">#endif </span><span class="comment">// _HARDWARE_STRUCTS_SCB_H</span></div>
<div class="line"><a id="l00074" name="l00074"></a><span class="lineno">   74</span> </div>
<div class="ttc" id="aaddress__mapped_8h_html"><div class="ttname"><a href="address__mapped_8h.html">address_mapped.h</a></div></div>
<div class="ttc" id="astructarmv6m__scb__hw__t_html"><div class="ttname"><a href="structarmv6m__scb__hw__t.html">armv6m_scb_hw_t</a></div><div class="ttdef"><b>Definition:</b> scb.h:26</div></div>
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